Memory chips are small, sensitive and consume small amounts of electrical power to perform on/off switching functions in individual bit cells. Bit cell switching and state retention operations can be disrupted by particles from outer space passing through the memory at the speed of light. Error checking and correction is technology that allows computers to correct memory errors. A popular type of error checking and correction commonly used in memory modules is single bit error correction, often referred to as check bits or error correction codes (ECC). The check bits enables detection and correction of single-bit errors. The check bits also enables detection of two-bit and some multiple bit errors, but is unable to correct such multi-bit errors.
For each data item sent across the memory bus, check bits are generated according to a correction technique. The check bits are then stored in the memory with the original data. The system uses the check bits to determine if the data is correct, and if not, locate and correct the single-bit error. The check bits are transferred with the original data. Therefore, an error checking and correction memory is wider then the non-error checking and correction memory. The number of check bits depends on a size of the data for correction. Table I illustrates the number of check bits as a function of the number of original data bits.
TABLE IOriginal data widthNumber of check bits(bits)Number of check bitsper data bitsXY(X) = log(X) + 2X/Y(X) 850.6251660.3753270.218756480.125128 90.0703125As shown in the table, as the number data bits increases, the number of check bits increases while the ratio of check bits per data bits decreases.
Referring to FIG. 1, a functional block diagram 10 of a convention memory write using check bits is shown. A conventional memory 12 is enlarged to store both the data bits 14 and an appropriate number of check bits 16 according to a data size that should be protected from errors. For example, if an error rate demands protecting the data from 1 bit error in every 8 bits (1 byte), error checking and correction processes 18a-18d operate on each byte of write data (i.e., 32 bits total). In the example, 5 check bits are added to every 8 bits of write data prior to storage in the memory 12.
Referring to FIG. 2, a functional block diagram 20 of a convention memory read using check bits is shown. Both the original data and the associated check bits are read from the memory 12 and presented to the error checking and correction processes 18a-18d. The error checking and correction processes 18a-18d determine if any errors are present in the received byte, and if so, correct the errors. A disadvantage of the conventional reads 20 and writes 10 is that a relatively large amount of the memory 12 is consumed by the check bits.